![]() It allows to encode a wider set of timings to achieve better performance and compatibility. Unlike Intel XMP, AMD EXPO is marketed as an open, license and royalty-free standard for describing memory kit parameters, such as operating frequency, timings and voltages. Additionally, Zen 4 supports new AMD EXPO SPD profiles for more comprehensive memory tuning and overclocking by the RAM manufacturers. On desktop and server platforms, Zen 4 supports only DDR5 memory, with support for DDR4 dropped. Zen 4 marks the first utilization of the 5 nm process for x86-based desktop processors. Zen 4's I/O die includes integrated RDNA 2 graphics for the first time on any Zen architecture. Previously, the I/O die on Zen 3 was built on GlobalFoundries' 14 nm process for Epyc and 12 nm process for Ryzen. Like its predecessor, Zen 4 in its Desktop Ryzen variants features one or two Core Complex Dies (CCDs) built on TSMC's 5 nm process and one I/O die built on 6 nm. Zen 4 powers Ryzen 7000 mainstream desktop processors (codenamed "Raphael") and will be used in high-end mobile processors (codenamed "Dragon Range"), thin & light mobile processors (codenamed "Phoenix"), as well as Epyc 9004 server processors (codenamed "Genoa" and "Bergamo"). It is the successor to Zen 3 and uses TSMC's N5 process for CCDs. We will see more of these area-saving techniques going forward as SRAM area scaling flatlines.Zen 4 is the codename for a CPU microarchitecture designed by AMD, released on September 27, 2022. While this is not as flexible as two independent access ports, the area reduction is significant enough for AMD to adopt this technology for Zen 4c. From the description, we see that TSMC is able to simulate a dual-port bitcell by doing a sequential read-and-write operation in the same clock cycle. TSMC will be presenting further details on this new bitcell at VLSI 2023 in June, which SemiAnalysis will be attending. AMD has replaced these 8T dual-port bitcells with a new 6T pseudo dual-port bitcell developed by TSMC. Zen 4c has a reduction in SRAM area within the core itself, as AMD has switched to using a new type of SRAM bitcell. One can say that AMD’s Zen 4c ‘looks like an ARM Core’.ģ. By merging those partitions from Zen 4, the regions can be packed closer together, adding another avenue of area saving by further boosting standard cell density. there are numerous partitions for each logical block within the core, but this is drastically reduced in Zen 4c with just 4 partitions (L2, Front End, Execution, FPU). With most designs nowadays being limited by routing density and congestion, a lower operating clock enables designers to squeeze signal paths closer together and improve standard cell density.Ģ. With a lower clock target, designers have more working room with the design of critical paths, simplifying timing closure and reducing the number of additional buffer cells required to clear relaxed timing constraints. ![]() Even with the same core design on the same node, there is a choice with the area of the core and the clock speed achievable on it. Here is a Speed vs Area curve for an ARM Cortex-A72 CPU Core synthesized on TSMC’s N5 and N3E nodes. ![]() lowering the clock target of a design can lead to reduced area when the core is synthesized. We detail the three key techniques of device Physical Design that enables this.ġ. Zen 4c’s CCD design area is just 72.7mm², not even 10% bigger! Keep in mind that there are double the cores, double the L2 cache, and the same amount of 元 cache on each die. This is the design area without die seal and scribe lines at the edges. At ISSCC 2023, AMD disclosed Zen 4’s CCD to be 66.3mm². 16 Zen 4c cores are barely larger than 8 Zen 4 cores. ![]()
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